A 60-GHz Differential Power Amplifier in a 90nm CMOS Technology
نویسندگان
چکیده
This paper describes a 60-GHz differential power amplifier (PA) designed in a 120-GHz fT 90nm CMOS technology. It consists of three identical differential cascode stages with inter-stage matching implemented by wide-gap coplanar waveguide (CPW) structures and M6M5 plate capacitors. A double-stub network realized by CPWs provides more design freedom for the input matching. Load-pull simulation generates an optimal differential load of 26.6 + j69.3Ω, and the output matching network transforms a differential 100Ω to this optimum impedance. High-Q M6/M5 capacitors in parallel with 5pF MOS capacitors decouple the supply and gate bias of cascode transistors for robust design. The simulated peak small-signal gain is 32.8dB and drops to 22dB at the maximum output power of 12dBm. At 62GHz, the peak PAE is 10.8%, and the -1dB compression point and IIP3 is around -22.8dBm and -15.8dBm, respectively. The die size is 1.18×1.78mm2, and the amplifier consumes 100mA from a 1.5 V supply. Compared to several mm-wave PAs from recent literature, this PA provides superior linear and saturated power gain though operating at the lowest supply voltage. Keywords— millimeter wave, differential power amplifier, CMOS power amplifier, coplanar waveguide, load pull
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